1. Technical Field
Embodiments of the present disclosure generally relate to integrated circuits, and more particularly to semiconductor devices generating test data patterns.
2. Related Art
Semiconductor devices operating with double data rate (DDR) transfers data on both the rising and falling edges of clock signals to increase their data rate. Extensions of this technique include, for example, a double data rate second generation (DDR2) standard and a double data rate third generation (DDR3) standard providing four bit data transfers or eight bit data transfers per cycle. However, an increase in data rate may result in an increase in bit error rate. Therefore, many techniques are being used to tolerate high error rates and to improve the reliability of data transmission.
One of the techniques is to generate codes capable of detecting occurrence of errors and/or correcting errors and transmit the codes with the data being transmitted to improve the reliability of data transmission. For example, an error detection code (EDC) may detect errors, and an error correction code (ECC) may correct the errors and restore the original data.